Portable personal computers (PCs) were first introduced in the early 1980s and have since enjoyed great commercial success and consumer acceptance. As the portable PC market has grown, users have begun to demand lighter weight, lower volume PCs which can be used for longer periods of time between battery charges. Meeting these demands has proved challenging in view of the fact that most portable PCs now support peripheral devices previously available only on desktop PCs. The additional peripherals greatly increase overall power consumption, making it difficult to achieve an optimal level of functionality while maintaining an acceptable battery life. Furthermore, although for reasons other than maximizing battery life, it has become desirable to more efficiently manage power consumption of desktop PCs in order to minimize overall operating costs.
One solution has been to design power management routines which cause certain I/O and peripheral devices to operate in the lowest possible power consumption state with respect to present demands on the device. For example, when the central processing unit (CPU) is not executing a program, its power consumption can be reduced considerably by decreasing the speed at which it operates. Further examples include turning off the LCD backlight or blanking the monitor screen after a period of keyboard inactivity and stopping the hard-disk drive motor after the drive has not been accessed for a preset interval of time.
In general, power management systems use interrupts to communicate to the central processing unit (CPU) of the PC that certain I/O devices should be powered down. The control logic necessary to implement the power management functions is accessed through the ROM basic input/output system (BIOS) software. For example, U.S. Pat. No. 4,980,836 to Carter discloses a power management system in which the activity of certain I/O devices is monitored and timers associated each device are reset each time the corresponding device is accessed. When a device has remained inactive for a predetermined interval of time, a non-maskable interrupt (NMI) is sent by power management circuitry to the CPU. Upon receiving the NMI, the CPU stops processing and executes the interrupt service code, i.e. places the device in its low power consumption state. The CPU then resumes processing from the point at which the interrupt occurred.
While the Carter system is functional in a DOS environment, it is not compatible and will not operate with protected mode operating systems and applications, such as Microsoft Windows, Unix and OS/2. Carter stores its power management control logic in ROM-BIOS, which is inherently limited to a 16-bit "real mode" operation and cannot operate in the 32-bit "protected mode" available with the Intel 80286 and more advanced 80X86 microprocessors. Protected mode operating systems and applications bypass the ROM-BIOS software, substituting their own BIOS therefor. As a result, hardware specific power management functions that are inserted into ROM-BIOS are lost when protected mode operating systems and applications are implemented.
Further, and perhaps more importantly, while a NMI is not problematic within a DOS environment, in a Windows environment, a NMI signals a fatal parity error, causing further input and output to be inhibited. For this mason, the power management system of Carter and those similar to it must be disabled prior to executing protected mode programs. Clearly, this result is unsatisfactory, especially in view of the growing popularity of Windows and Windows-based applications.
Other power management systems have been developed which are compatible with Windows and other protected mode programs. These systems use an interrupt other than a NMI, such as interrupt 15H (INT 15H). These systems are also deficient in that the use of INT 15H is not exclusive, making it impossible to determine whether the interrupt code which is ultimately executed is that of the power management system or of another applications program. Moreover, special device drivers and interrupt service code specific to the particular hardware and operating system version must be inserted into the program in order to implement power management functions. As a result, these systems must be designed specifically for and may be implemented only with a particular combination of hardware and operating system software.
Another attempt at making power management systems compatible with protected mode programs has involved the use of microprocessors that support a system management interrupt (SMI). An example of such a processor includes the Intel SL. A SMI, unlike a NMI, is operable in protected mode because it does not map with the operating system. When the CPU receives a SMI, it saves a large number of internal registers, executes thousands of lines of code, and then restores the registers. As a result, using a SMI to implement power management will prove to be prohibitively slow with respect to certain CPU activities. For example, if the CPU receives a SMI while performing a serial I/O transfer, some data will be lost during the time it takes the CPU to save its state, service the interrupt and resume processing. To avoid this result, the power management functions must be disabled whenever a serial transfer or other time critical operation is to be performed.